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? 1998 integrated device technology, inc. 1 commercial temperature range integrated device technology, inc. features ? dual issue super-scalar execution core, executing at high-frequency - 250 mhz frequency - dual issue floating-point alu operations with other instruction classes - traditional 5-stage pipeline, minimizes load and branch latencies - single cycle repeat rate for most floating point alu operations ? high level of performance for a variety of applications - high-performance 64-bit integer unit achieves 330 dhrystone mips (dhrystone 2.1) - ultra high-performance floating-point accelerator, directly implementing single- and double-precision operations achieves 500mflops - extremely large on-chip primary caches - on-chip secondary cache controller ? large, efficient on-chip caches - 32kb instruction cache, 32kb data cache - 2-set associative in each cache - virtually indexed and physically tagged to minimize cache flushes - write-back and write-through selectable on a per page basis - critical word first cache miss processing - supports back-to-back loads and stores in any com- bination at full pipeline rate ? high-performance memory system - large primary caches integrated on-chip - secondary cache control interface on-chip - high-frequency 64-bit bus interface runs up to 100mhz - aggregate bandwidth of on-chip caches, system interface of 5gb/s - high-performance write protocols for graphics and data communications ? mips-iv 64-bit isa for improved computation - compound floating-point operations for 3d graphics and floating-point dsp - conditional move operations ? compatible with a variety of operating systems - windows? ce - numerous mips-compatible real-time operating sys- tems ? uses input system clock, with processor pipeline clock multiplied by a factor of 2-8 ? large on-chip tlb ? active power management, including use of wait operation multi-issue 64-bit microprocessor june, 1998 block diagram the idt logo is a registered trademark and orion, r4600, r4640, r4650, r4700, r5000, rv5000, and riscontroller are trademarks o f integrated device technology, inc. mips is a registered trademark of mips computer systems, inc. instruction tag b itlb physical write buffer dva iva floating-point control integer control dbus tag auxtag intibus fpibus abus data set a store buffer phase lock loop data tag a instruction set a dtlb physical instruction select integer instruction register fp instruction register data set b read buffer address buffer instruction tag a sysad control floating point register file unpacker/packer joint tlb coprocessor 0 system/memory control pc incrementer branch adder instruction tlb virtual program counter load aligner integer register file integer/address adder data tlb virtual shifter/store aligner logic unit integer multiply, divide floating point madd,add,sub, cvt div, sqrt instruction set b idt rc5000
idt rc5000 commercial temperature range 2 description the rc5000 serves many performance critical embedded applications, such as high-end internet- working systems, color printers, and graphics terminals. the rc5000 is optimized for high-performance appli- cations, with special emphasis on system bandwidth and floating point operations, through integration of high- performance computational units and a high-performance memory hierarchy. for this class of application, the result is a relatively low-cost cpu capable of approximately 330 dhrystone mips. idts objectives in offering the rc5000 include: ? offering a high performance upgrade path to existing embedded customers in the internetworking, office automation and visualization markets. ? providing a significant improvement in the floating- point performance currently available in a moderately priced mips cpu. ? providing improvements in the memory hierarchy of desktop systems by using large primary caches and integrating a secondary cache controller. ? enabling improvements in performance through the use of the mips-iv isa. instruction issue mechanism the rc5000 recognizes two general classes of instructions for multi-issue: ? floating-point alu ? all others these instruction classes are pre-decoded by the rc5000, as they are brought on-chip. the pre-decoded information is stored in the instruction cache. assuming that there are no pending resource conflicts, the rc5000 can issue one instruction per class per pipeline clock cycle. note that this broad separation of classes insures that there are no data dependencies to restrict multi-issue. however, long-latency resources in either the floating- point alu (e.g. div or sqrt instructions) or instructions in the integer unit (such as multiply) can restrict the issue of instructions. note that the r5000 does not perform out- of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. there are no alignment restrictions on dual-issue instruction pairs. the rc5000 fetches two instructions from the cache per cycle. thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, since the instruction cache only performs aligned fetches. instruction set architecture the rc5000 implements the mips-iv 64-bit isa, including cp1 and cp1x functional units (and their instruction set). integer pipeline the rc5000 is a limited dual-issue machine that utilizes a traditional 5-stage integer pipeline. this basic integer pipeline of the rc5000 is illustrated in figure 1. the integer instruction execution speed is tabulated (in number of pipeline clocks) as follows: the rc5000s short pipeline keeps the load and branch latencies very low. the caches contain special logic that allows any combination of loads and stores to execute in back-to-back cycles without requiring pipeline slips or stalls. (this presumes, of course, that the opera- tion does not miss in the cache.) operation latency repeat load 2 1 store 2 1 mult/multu 8 8 dmult/dmultu 12 12 div/divu 36 36 ddiv/ddivu 68 68 other integer alu 1 1 branch 2 2 jump 2 2
idt rc5000 commercial temperature range 3 rc5000 computational units the rc5000 contains the following computational units: integer alu . the rc5000 implements a full, single-cycle 64-bit alu for all integer alu functions other than multiply and divide. bypassing is used to support back-to-back alu operations at the full pipeline rate, without requiring stalls for data dependencies. integer multiply/divide unit . this unit is separated from the primary alu, to allow these longer latency operations to run in parallel with other operations. the pipeline stalls only if an attempt to access the hi or lo registers is made before the operation completes. floating-point alu . this unit is responsible for all cp1/cp1x alu operations other than div/sqrt. the unit is pipelined to allow a single-cycle repeat rate for single-precision operations floating-point div/sqrt unit . this unit is separated from the other floating-point alu, so that these long latency operations do not prevent the issue of other floating point operations. in addition, the rc5000 implements separate logical units to implement loads, stores, and branches. electrical specifications operating frequency the input clock operates in a frequency range of 33mhz to 100mhz. the pipeline frequency for the rc5000 is 2 to 8 times the input clock (up to the maximum for the speed grade of cpu). thermal considerations the rc5000 utilizes special packaging techniques, to improve the thermal properties of high-speed processors. the rc5000 is packaged using cavity down packaging in a 223-pin pga package with integral thermal slug, and a 272-pin bga package. these packages effectively dissipate the power of the cpu, increasing device reliability. i 0 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 1 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 2 1i 2i 1r 2r 1a 2a 1d 2d 1w ??? i 3 1i 2i 1r 2r 1a 2a 1d ??? i 4 1i 2i 1r 2r 1a ??? one cycle key to figure 1i-1r instruction cache access 2i instruction virtual to physical address translation 2a-2d data cache access and load align 1d data virtual to physical address translation 1d-2d virtual to physical address translation 2r register file read 2r bypass calculation 2r instruction decode 2r branch address calculation 1a issue or slip decision 1a-2a integer add, logical, shift 1a data virtual address calculation 2a store align 1a branch decision 2w register file write figure 1. r5000 integer pipeline stages
idt rc5000 commercial temperature range 4 the rc5000 utilizes an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing. due to the heat-spreading effect of the aluminum, the package allows for an efficient thermal transfer between the die and the case. the aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the pcb for a given temperature. even nominal amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. the rc5000 is guaranteed in a case temperature range of 0 to +85 c. the type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient ( ? ca ) of the given package. the following equation relates ambient and case temperatures: t a = t c - p * ? ca where p is the maximum power consumption at hot temperature, calculated by using the maximum i cc speci- fication for the device. typical values for ? ca at various airflows are shown in table 1. table 1. thermal resistance ( ? ca) at various airflows note: the rc5000 implements advanced power management to substantially reduce the average power dissipation of the device. this operation is described in the idt79rv5000 risc microprocessor reference manual. ? ca airflow (ft/min) 0 200 400 600 800 1000 pga 167532.52 bga 146432.52 data sheet revision history changes to version dated january 1996: pin description section: - corrected pin list for clock/control, initialization, and secondary cache interfaces. advance pin-out section: - changed pins aa19 and aa21 from vcc to vss. changes to version dated march 1997: - upgraded data sheet status from preliminary to final. - added section on thermal considerations - added section on absolute maximum ratings changes to version dated june 1997: - revised power consumption and system interface parameters changes to version dated september 1997: - added user notation on boot mode bits 20 and 33 for 200 mhz frequency changes to version dated june 1998: - added 250 mhz; changed naming conventions
idt rc5000 commercial temperature range 5 logic symbol figure 1. rc5000 logic symbol sysad(63:0) sysadc(7:0) syscmd(8:0) syscmdp validin* validout* extrqst* release* wrrdy* bigendian sysclock vccok coldreset* reset* vccp vssp vcc vss scword (1:0) sctce* sctde* sctoe* scclr* scdce* scdoe* scline (15:0) scmatch int (5:0)* nmi* modeclock modein jtdi jtdo jtms jtck sccwe* initialization interface secondary cache interface interrupt system interface clock interface rc5000 logic symbol 64 8 9 16 6 rdrdy* jtag interface interface 2 34 34 scvalid
idt rc5000 commercial temperature range 6 pin description rc5000 implements a bus similar to that of the rc4700. table 2 lists and describes the rc5000 signals. pin name type description system interface : extrqst* input external request. signals that the system interface needs to submit an external request. release* output release interface. signals that the processor is releasing the system interface to slave state rdrdy* input read ready. signals that an external agent can now accept a processor read. wrrdy* input write ready. signals that an external agent can now accept a processor write request. validin* input valid input. signals that an external agent is now driving a valid address or data on the sysad bus and a valid com- mand or data identifier on the syscmd bus. validout* output valid output. signals that the processor is now driving a valid address or data on the sysad bus and a valid com- mand or data identifier on the syscmd bus. sysad(63:0) input/output system address/data bus. a 64-bit address and data bus for communication between the processor and an external agent. sysadc(7:0) input/output system address/data check bus. an 8-bit bus containing parity check bits for the sysad bus during data bus cycles. syscmd(8:0) input/output system command/data identifier bus. a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp input/output reserved system command/data identifier bus parity. for the rc5000, unused on input and zero on output. clock/control interface: sysclock input master clock. master clock input at the bus frequency. the pipeline clock is derived by multiplying this clock up. vccp input quiet vcc for pll. quiet vcc for the internal phase locked loop. vssp input quiet vss for pll. quiet vss for the internal phase locked loop. interrupt interface: int(5:0)* input interrupt. six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* input non-maskable interrupt. non-maskable interrupt, ored with bit 6 of the interrupt register. jtag interface: jtdi input jtag data in. connected directly to jtdo. no jtag implemented; should be pulled high. jtck input jtag clock input. unused input; should be pulled high. jtdo output jtag data out. connected directly to jtdi. if no external scan used, this is a no connect. table 2. rc5000 signal names and descriptions (page 1 of 2)
idt rc5000 commercial temperature range 7 jtms input jtag command. unused input. should be pulled high. initialization interface: vccok input vcc is ok. when asserted, this signal indicates to the rc5000 that the power supply has been abovevcc mini- mum for more than 100 milliseconds and will remain stable. the assertion of vccok initiates the read- ing of the boot-time mode control serial stream. coldreset* input cold reset. this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted syn- chronously with sysclock. reset* input reset. this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchro- nously for a cold reset, or synchronously to initiate a warm reset. reset must be synchronously de- asserted with sysclock. modeclock output boot mode clock. serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. modein input boot mode data in. serial boot-mode data input. bigendian input endian mode select. allows the system to change the processor addressing mode without rewriting the mode rom. if endi- anness is to be specified by using the bigendian pin, program mode rom bit 8 to 0; if endianness is to be specified by the mode rom, ground the bigendian pin. secondary cache interface: scclr* output secondary cache block clear. clears all valid bits in those tag rams which support this function. sccwe*(1:0) output secondary cache write enable. asserted during writes to the secondary cache scdce*(1:0) output data ram chip enable. chip enable for secondary cache data ram scdoe* input data ram output enable. asserted by the external agent to enable data onto the sysad bus scline (15:0) output data ram output enable. cache line index for secondary cache scmatch input secondary cache tag match. asserted by tag ram on secondary cache tag match sctce* output secondary cache tag ram chip enable. chip enable for secondary cache tag ram. sctde* output secondary cache tag ram data enable. data enable for secondary cache tag ram. sctoe* output secondary cache tag ram output enable. tag ram output enable for secondary cache tag rams scword (1:0) input/output secondary cache word index. determines correct double-word of secondary cache index scvalid input/output secondary cache valid. always driven by the cpu except during a cache probe operation, when it is driven by the tag ram. pin name type description table 2. rc5000 signal names and descriptions (page 2 of 2)
idt rc5000 commercial temperature range 8 absolute maximum ratings 1 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = C2.0v for pulse width less than 15ns. v in should not exceed v cc +0.5 volts. 3. when v in < 0v or v in > v cc. 4. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. recommended operation temperature and supply voltage symbol rating rc5000 3.3v 5% unit commercial v term terminal voltage with respect to gnd C0.5 (2) to +4.6 v t c operating temperature (case) 0 to +85 c t bias case temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c i in dc input current 20 (3) ma i out dc output current 50 (4) ma grade temperature gnd rc5000 v cc commercial 0 c to +85 c (case) 0v 3.3v 5%
idt rc5000 commercial temperature range 9 ac electrical characteristics (v cc = 3.3v 5%; t case = 0 c to +85 c ) clock parametersrc5000 capacitive load derationrc5000 power consumptionrc5000 system interface parameters rc5000 parameter symbol 180mhz 200mhz ? 250mhz ?# units min max min max min max sysclock high t schigh 3 3 2.5 ns sysclock low t sclow 3 3 2.5 ns sysclock frequency 33 90 33 100 33 125 mhz sysclock period t scp 11.1 30 10 30 8 30 ns sysclock rise time t scrise 2.5 2 2ns sysclock fall time t scfall 2.5 2 2ns modeclock period t modeckp 256 t scp 256 t scp 256 t scp ns parameter symbol test conditions 180mhz 200mhz ? 250mhz ?# units minmaxminmaxminmax load derate c ld 222ns/25pf parameter 180mhz 200mhz ? 250mhz ?# conditions max max max system condition 180/45mhz 200/50mhz 250/62.5mhz i cc standby 120ma 120ma 120ma c l = 50 pf active 1100ma 1300ma 1800ma c l = 50pf pipelined writes or write re-issue t c = 25 o c parameter symbol test conditions 180mhz 200mhz ? 250mhz ?# units min max min max min max data output t dm = min t do = max mode 14..13 = 10 (fastest) 1.5* 7 1.5* 5 1.5* 5 ns mode 14..13 = 01 (slowest) 1.5* 11 1.5* 11 1.5* 11 ns
idt rc5000 commercial temperature range 10 boot time interface parametersrv5000 ? boot mode bits 20 and 33 must be set to 1 for operation at this frequency. # preliminary information for 250mhz. data input t ds t rise = 3ns t fall = 3ns 1.5 1.5 1.5 ns t dh 0.5 0.5 0.5 ns *guaranteed by design parameter symbol test conditions 180mhz 200mhz ? 250mhz ?# units minmaxminmaxminmax mode data setup t ds 4 4 4 master clock cycle mode data hold t dh 0 0 0 master clock cycle parameter symbol test conditions 180mhz 200mhz ? 250mhz ?# units min max min max min max
idt rc5000 commercial temperature range 11 dc electrical characteristics (v cc = 3.3v 5%; t case = 0 c to +85 c) ? boot mode bits 20 and 33 must be set to 1 for operation at this frequency. # preliminary information for 250mhz. parameter 180mhz 200mhz ? 250mhz ?# conditions min max min max min max v ol 0.1v 0.1v 0.1v |i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v |i out |= 4ma v oh 2.4v 2.4v 2.4v v il C0.5v 0.2v cc C0.5v 0.2v cc C0.5v 0.2v cc v ih 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v i in 10ua 10ua 10ua 0 v in v cc c in 10pf 10pf 10pf c io 10pf 10pf 10pf c clk 10pf 10pf 10pf i/o leak 20ua 20ua 20ua input/output leakage
idt rc5000 commercial temperature range 12 physical specifications the rc5000 is available in two packages, the 223-pin cpga and the 272-ball sbga. information on the cpga package is shown in figure 2 and table 3; information on the sbga package is shown in figure 3 and table 4. figure 2. rc5000 cpga pin orientation (bottom view) a b c d e f g h j k t u l m n p r v 1 23456789101112131415161718 223-pin cpga
idt rc5000 commercial temperature range 13 223-pin cpga pinout pkg pin function pkg pin function pkg pin function pkg pin function pkg pin function pkg pin function a2 vcc c5 sysadc[6] e18 vcc k17 vssp r6 sysad[51] u9 sysad[63] a3 vss c6 sysad[16] f1 vcc k18 vss r7 sysad[55] u10 sysad[13] a4 vcc c7 sysad[50] f2 reserved l1 vss r8 sysad[27] u11 sysad[11] a5 vss c8 sysad[22] f3 scvalid l2 syscmd[8] r9 sysad[31] u12 sysad[9] a6 vss c9 sysad[24] f4 int[1]* l3 syscmd[7] r10 sysad[43] u13 sysad[37] a7 vcc c10 sysad[28] f15 scdce[0]* l4 syscmd[5] r11 sysad[39] u14 sysad[3] a8 vss c11 sysad[62] f16 sccwe[0]* l15 scline[12] r12 sysad[35] u15 scword[0] a9 vcc c12 sysad[44] f17 sctde* l16 scline[14] r13 sysad[1] u16 vcc a10 vss c13 sysad[10] f18 vss l17 scline[15] r14 scword[1] u17 vss a11 vcc c14 sysad[38] g1 vss l18 vcc r15 scline[0] u18 vss a12 vss c15 sysad[4] g2 reserved m1 vcc r16 scline[3] v1 vss a13 vcc c16 sysad[34] g3 reserved m2 syscmd[6] r17 scline[6] v2 vss a14 vss c17 sysad[2] g4 reserved m3 syscmd[4] r18 vss v3 vcc a15 vss c18 vss g15 scclr* m4 syscmd[1] t1 vss v4 vss a16 vcc d1 vss g16 sctce* m15 scline[8] t2 sysad[15] v5 vss a17 vss d2 int3* g17 modein m16 scline[10] t3 sysad[47] v6 vcc a18 vss d3 int5* g18 vcc m17 scline[13] t4 sysad[17] v7 vss b1 vss d4 release* h1 vcc m18 vss t5 sysad[19] v8 vcc b2 vss d5 vcc h2 reserved n1 vss t6 sysad[23] v9 vss b3 vcc d6 sysadc[2] h3 reserved n2 syscmd[3] t7 sysad[57] v10 vcc b4 sysadc[4] d7 sysad[48] h4 reserved n3 syscmd[2] t8 sysad[29] v11 vss b5 sysadc[0] d8 sysad[52] h15 vccok n4 sysadc[7] t9 vcc v12 vcc b6 sysad[18] d9 sysad[56] h16 modeclock n15 scline[5] t10 sysad[45] v13 vss b7 sysad[20] d10 sysad[60] h17 sysclock n16 scline[7] t11 sysad[41] v14 vcc b8 sysad[54] d11 sysad[14] h18 vss n17 scline[11] t12 sysad[7] v15 vss b9 sysad[26] d12 sysad[42] j1 vss n18 vcc t13 sysad[5] v16 vss b10 sysad[58] d13 sysad[8] j2 wrrdy* p1 vcc t14 sysad[33] v17 vcc b11 sysad[30] d14 sysad[36] j3 validin* p2 syscmd[0] t15 reset* v18 vss b12 sysad[46] d15 coldreset* j4 extreq* p3 syscmdp t16 scline[1] b13 sysad[12] d16 sysad[0] j15 jtdo p4 sysadc[1] t17 vcc b14 sysad[40] d17 sctoe* j16 jtdi p15 scline[2] t18 vcc b15 sysad[6] d18 vcc j17 jtck p16 scline[4] u1 vcc b16 vss e1 vss j18 vcc p17 scline[9] u2 vcc b17 vcc e2 int[0]* k1 vcc p18 vss u3 vss b18 vcc e3 int[2]* k2 scmatch r1 vcc u4 sysad[21] c1 vcc e4 int[4]* k3 rdrdy* r2 sysadc[5] u5 sysad[53] c2 vcc e15 sysad[32] k4 scdoe* r3 sysadc[3] u6 sysad[25] c3 validout* e16 scdce[1]* k15 jtms r4 bigendian u7 sysad[59] c4 nmi* e17 sccwe[1]* k16 vccp r5 sysad[49] u8 sysad[61] table 3. 223-pin cpga pinout
idt rc5000 commercial temperature range 14 figure 3. ball grid array package (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 272-ball sbga 19 20 21 a b c d e f g h j k t u l m n p r v w y aa
idt rc5000 commercial temperature range 15 272-ball sbga pinout pkg pin function pkg pin function pkg pin function pkg pin function pkg pin function pkg pin function aa1 vss b5 sysad0 d9 vss j2 sysad46 p21 sysad55 w1 vss aa2 vcc b6 sctoe* d10 vcc j3 sysad14 r1 vss w2 vcc aa3 vss b7 scclr* d11 vccp j4 vss r2 sysad18 w3 vcc aa4 validout* b8 sctde* d12 vcc j18 vss r3 sysad48 w4 vcc aa5 vss b9 modeclock d13 vss j19 sysad9 r4 vcc w5 int*5 aa6 int*0 b10 jtdi d14 vcc j20 sysad41 r18 vcc w6 int*4 aa7 vss b11 jtck d15 vcc j21 vss r19 sysad53 w7 int*1 aa8 reserved b12 n/c d16 vss k1 sysad60 r20 sysad23 w8 reserved aa9 vss b13 scline14 d17 vcc k2 sysad30 r21 vss w9 reserved aa10 wrrdy* b14 scline10 d18 vss k3 sysad62 t1 sysad16 w10 reserved aa11 vss b15 scline9 d19 vcc k4 vcc t2 sysadc0 w11 validin* aa12 scmatch b16 scline6 d20 vcc k18 vcc t3 sysadc2 w12 scdoe* aa13 vss b17 scline3 d21 vcc k19 sysad11 t4 vss w13 syscmd7 aa14 syscmd6 b18 scline1 e1 vss k20 sysad43 t18 vss w14 syscmd4 aa15 vss b19 vcc e2 sysad36 k21 sysad13 t19 sysad19 w15 syscmd1 aa16 syscmd2 b20 vcc e3 sysad4 l1 vss t20 sysad51 w16 sysadc7 aa17 vss b21 vcc e4 vcc l2 sysad58 t21 sysad21 w17 sysadc5 aa18 sysadc3 c1 vss e18 vcc l3 sysad28 u1 vss w18 sysad47 aa19 vss c2 vcc e19 scword1 l4 vcc u2 sysadc4 w19 bigendian aa20 vcc c3 coldreset* e20 scword0 l18 vcc u3 sysadc6 w20 vcc aa21 vss c4 sysad34 e21 vss l19 sysad45 u4 vcc w21 vss a1 vss c5 scdce*1 f1 sysad8 l20 sysad63 u18 vcc y1 vcc a2 vcc c6 scdce*0 f2 sysad38 l21 vss u19 sysad17 y2 vcc a3 vss c7 sccwe*0 f3 sysad6 m1 sysad26 u20 sysad49 y3 vcc a4 sysad32 c8 sctce* f4 vss m2 sysad56 u21 vss y4 release* a5 vss c9 modein f18 vss m3 sysad24 v1 vcc y5 int*3 a6 sccwe*1 c10 jtdo f19 sysad1 m4 vcc v2 vcc y6 int*2 a7 vss c11 vssp f20 sysad33 m18 vcc v3 vcc y7 scvalid a8 vccok c12 jtms f21 sysad3 m19 sysad29 v4 vss y8 reserved a9 vss c13 scline13 g1 vss m20 sysad61 v5 nmi* y9 reserved a10 masterclk c14 scline11 g2 sysad10 m21 sysad31 v6 vss y10 reserved a11 vss c15 scline8 g3 sysad40 n1 vss v7 vcc y11 extrqst* a12 scline15 c16 scline5 g4 vcc n2 sysad54 v8 vcc y12 rdrdy* a13 vss c17 scline4 g18 vcc n3 sysad22 v9 vss y13 syscmd8 a14 scline12 c18 scline0 g19 sysad35 n4 vss v10 vcc y14 syscmd5 a15 vss c19 reset* g20 sysad5 n18 vss v11 vcc y15 syscmd3 a16 scline7 c20 vcc g21 vss n19 sysad27 v12 vcc y16 syscmd0 a17 vss c21 vss h1 sysad42 n20 sysad59 v13 vss y17 syscmdp a18 scline2 d1 vcc h2 sysad44 n21 vss v14 vcc y18 sysadc1 a19 vss d2 vcc h3 sysad12 p1 sysad50 v15 vcc y19 sysad15 a20 vcc d3 vcc h4 vcc p2 sysad52 v16 vss y20 vcc a21 vss d4 vss h18 vcc p3 sysad20 v17 vcc y21 vcc b1 vcc d5 vcc h19 sysad7 p4 vcc v18 vss b2 vcc d6 vss h20 sysad39 p18 vcc v19 vcc b3 vcc d7 vcc h21 sysad37 p19 sysad25 v20 vcc b4 sysad2 d8 vcc j1 vss p20 sysad57 v21 vcc table 4. 272-ball sbga pinout
idt rc5000 commercial temperature range 16 integrated device technology, inc. reserves the right to make changes to the specifications in this data sheet in order to impr ove design or performance and to supply the best possible product. integrated device technology, inc. 2975 stender way, santa clara, ca 95054-3090 telephone: (408) 727-6116 fax 408-492-8674 ordering information valid combinations idt79rv5000 - 180, 200mhz g cpga package idt79rv5000 - 180, 200, 250mhz bs sbga package idt79 yy xxxx 999 a a operating voltage device ty p e speed package temp range/ process 5000 180 200 blank commercial (0 c to +85 c case) 180 mhz pclk 200 mhz pclk multi-issue 64-bit microprocessor 3.3+/-5% 272-pin sbga 223-pin cpga g bs rv 250 250 mhz pclk

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